The present invention relates generally to a semiconductor memory device and more particularly to a semiconductor memory device and a method of detecting cell current for outputting data during a read operation.
In order to reduce the chip size of a read only memory (ROM), memory array architecture can be based on a flat cell. A flat cell may not have element isolation regions in the cell array. Thus, memory cells along a row can be connected in series.
Referring now to FIG. 7, a conventional ROM having a cell array using a flat cell is set forth in a block schematic diagram and designated by the general reference character 700. Conventional ROM 700 includes a memory array 701, a sense amplifier 702, a y-selector 703, precharge circuits 704, a virtual ground (VG) selector 705, and a x-decoder 706.
The example illustrated in FIG. 7 is a read operation of a memory cell connected to digit line D2 and located between digit lines D2 and D1. In the read operation, based on an applied y-address, Y-selector 703 selectively connects a main digit line (in this example D2) to a sense amplifier 702 and selectively connects an adjacent main digit line (in this example D3) to precharge circuit 704. At this same time VG selector 705 connects virtual ground line VG1 to ground and virtual ground line VG2 to precharge circuit 704.
Referring now to FIG. 8, a circuit schematic wiring diagram of the y-selector 703 of FIG. 7 is set forth. Y-selector includes a data selection section 802 and a precharge section 804.
Data selection section 802 includes data selection circuits (806 and 806xe2x80x2). It is understood that there are many data selection circuits but only data selection circuits (806 and 806xe2x80x2) are illustrated to avoid unduly cluttering the figure. Each data selection circuit operates in the same manner, thus only data selection circuit 806 will be discussed. Data selection circuit 806 receives y-selection signals (Y0 to Y7). Data selection circuit 806 includes data selection transistors (TD0 to TD7) connected between digit lines (D0 to D7) respectively and sense amplifer 702. Each data selection transistor (TD0 to TD7) receives a respective y-selection signal (Y0 to Y7) and selectively connects a digit line to a respective sense amplifier 702. In this case, y-selection signal Y2, is active (high), thus data selection transistor TD2 is conductive and electrically connects digit line D2 to sense amplifier 702. Thus, a data bit from a cell (not shown in FIG. 8) connected to digit line D2 is accessed. In this case, all other digit lines in the digit line group (D0, D1, and D3 to D7) are not connected to sense amplifier 702 because their corresponding data selection transistor (TD0, TD1, and TD3 to TD7) are turned off.
Precharge section 804 includes precharge selection circuits (808 and 808xe2x80x2). It is understood that there are many precharge selection circuits but only precharge selection circuits (808 and 808xe2x80x2) are illustrated to avoid unduly cluttering the figure. Each precharge selection circuit operates in the same manner, thus only data selection circuit 808 will be discussed. Precharge selection circuit 808 receives precharge selection signals (P0 to P7). Precharge selection circuit 808 includes precharge selection transistors (TP0 to TP7) connected between digit lines (D0 to D7) respectively and precharge circuit 704. Each precharge selection transistor (TP0 to TP7) receives a respective precharge selection signal (P0 to P7) and selectively connects a digit line to precharge circuit 704. In this case, precharge selection signal P3, is active (high), thus precharge selection transistor TP3 is conductive and electrically connects digit line D3 to precharge circuit 704. Thus, digit line D3 is precharged when a data bit from a cell (not shown in FIG. 8) connected to adjacent digit line D2 is accessed. In this case, all other digit lines in the digit line group (D0, D1, D2 and D4 to D7) are not connected to precharge circuit 704 because their corresponding precharge selection transistor (TD0, TD1, TD2, and TD4 to TD7) are turned off.
Referring now to FIG. 9, a circuit diagram showing an operating state of conventional semiconductor memory device 700 is set forth. For simplicity, the circuit diagram of FIG. 9, illustrates only a portion of the memory cell array 702 corresponding to digit lines (D2 to D5)
The conventional semiconductor memory 700 of FIG. 9, illustrates a read from memory cell 910. Memory cell 910 has been programmed with a low threshold voltage, such that when word line W01 is high, memory cell 910 is conductive or is an on-bit cell. Memory cells that are not conductive (off-bit cell) when their respective word line is high are denoted with an xe2x80x9cXxe2x80x9d. It can be seen that the memory cell adjacent to memory cell 910 and commonly connected to sub-digit line D22 is an off-bit cell.
FIG. 10 sets forth a truth table illustrating logic levels of y-selection signals (Y0 to Y7), precharge selection signals (P0 to P7), bank selection signals (BS0 and BS1) and ground selection lines (GS0 to GS3) when a predetermined memory cell column is selected. In the example illustrated in FIG. 9, memory cell 910 is selected. Memory cell 910 is in a memory cell column that corresponds with digit line D2 and BANK2. Thus, y-selection signal Y2, precharge signal P3, bank selection signal BS1, and ground selection line GS1 are all enabled (high).
When memory cell 910 is selected, word line W01 goes high and y-selection signal Y2, precharge signal P3, bank selection signal BS1, and ground selection line GS1 are all high. Also, main virtual ground line VG1 is connected to ground and main virtual ground line VG2 is connected to a precharge potential through precharge circuit 704. In this manner, selected memory cell 910 has a source electrically connected to ground through a VG selection transistor 902 and a drain electrically connected to sense amplifier 702 through bank selection transistor 906 and data selection transistor TD2.
In the case illustrated in FIG. 9, the cell adjacent to memory cell 910 is an off-cell, thus current flowing from precharge circuit 704 through the row of memory cells connected to word line W01 is blocked from sub-digit line D22 and memory cell 910. Therefore, in this case, a steady-state current ISA flowing through selected cell 910 is the same as the current flowing through digit line D2 and sensed by sense amplifier 702.
Referring now to FIG. 11, a circuit diagram showing an operating state of conventional semiconductor memory device 700 is set forth. The circuit diagram of FIG. 11, illustrates a case where the memory cell adjacent to selected memory cell 910 is an on-bit cell. In this case, selected memory cell 910 provides a current path from ground to sense amplifier 702, shown as ISA. However, selected memory cell 910 also provides current paths from ground to precharge circuit 704. These undesirable current paths are illustrated by dashed lines, where IPC0 is a current path to precharge circuit 704 through digit line D3 and IPC1 is a current path to precharge circuit 704 through VG selection transistor 904. In this case, the current flowing through selected cell 910 is given by the sum of current ISA0 flowing through selected digit line D2 and the currents IPC0 and IPC1 flowing from precharge circuit 704.
xe2x80x83ISA=ISA0+IPC0+IPC1
Referring now to FIG. 12, a graph is shown illustrating a simulation of currents in the memory cell configurations of FIGS. 9 and 11 over a range of operating voltages.
Waveform 1202 illustrates the current ISA as shown in FIG. 9 in which the cell adjacent to selected cell 910 is an off-bit cell. Waveform 1204 illustrates the current ISA0 as shown in FIG. 11 in which the cell adjacent to selected cell 910 is an on-bit cell. Waveform 1206 illustrates the current IPC0 as shown in FIG. 11. Waveform 1208 illustrates the current IPC1 as shown in FIG. 1.
The simulation results indicate that there is a difference of more than 7 microamperes (uA) or approximately 18% between waveforms 1202 (ideal case, FIG. 9) and 1204 (FIG. 11 case) at an operating voltage of 3.3 volts. It can also be seen that the minimum value of the sense amplifier current is less than 30 uA at 3.3 volts in the case of the configuration of FIG. 11.
A technique for improving the precision of the current detection by stabilizing the sense amplifier current has been disclosed in Japanese Patent Application Laid Open No. Hei 4-311900. However, when the fluctuation in the sense amplifier current is large, the circuit design can be difficult and highly restricted. Also, if the minimum sense amplifier current decreases, noise tends to introduce erroneous operation.
In view of the above discussion, it would be desirable to provide a semiconductor memory in which the minimum sense amplifier current is increased as compared to conventional approaches. Still further it would also be desirable to decrease the difference between the current flowing through the selected memory cell and the current detected by the sense amplifier.
According to the present embodiments, a semiconductor memory device includes a selection circuit electrically connecting a first and second digit line to a sense amplifier during a read operation and the sense amplifier can detect a data value stored in a selected memory cell by in accordance with the summation of currents on the first and second digit lines.
According to one aspect of the embodiments, the semiconductor memory device can include a plurality of memory cells having source/drain paths arranged in series where adjacent memory cell are electrically connected at a common source/drain node.
According to another aspect of the embodiments, the semiconductor memory device can include a plurality of word lines arranged in a first direction and the plurality of memory cells can be electrically connected to a word line.
According to another aspect of the embodiments, the semiconductor memory device can include a third digit line being electrically connected to a precharge circuit.
According to another aspect of the embodiments, the semiconductor memory device can include a first virtual ground line receiving a reference voltage and selectively coupled to a source of the selected memory cell during a read operation.
According to another aspect of the embodiments, the semiconductor memory device can include a second virtual ground line receiving a precharge voltage and being selectively coupled to a source/drain connection of unselected ones of the plurality of memory cells.
According to another aspect of the embodiments, a selection circuit can receive selection signals and selectively electrically connect a virtual ground line to source/drain connection of memory cells.
According to another aspect of the embodiments, a selection circuit can receive selection signals and selectively electrically connect digit lines to a sense amplifier.
According to another aspect of the embodiments, a selection circuit can receive selection signals and selectively electrically connect a digit line to a precharge circuit.
According to another aspect of the embodiments, memory cells can be chain linked in series and can be programmed to conduct simultaneously when selected. A predetermined selected memory cell can have a cell current that includes the summation of a first current flowing through a first digit line, a second current flowing through a second digit line and a third current flowing from a precharge voltage supplied by at least one of the plurality of virtual ground lines and the first and second currents can be greater than the third current.
According to another aspect of the embodiments, the predetermined selected memory cell current can include a fourth current flowing from a precharge circuit through a digit line and the first and second currents can be greater than the fourth current.
According to another aspect of the embodiments, a plurality of sub-digit lines can be coupled to a digit line through a bank selector circuit. The bank selector circuit can receive a bank selection signal to selectively electrically connect a sub-digit line to a digit line.
According to another aspect of the embodiments, a method of outputting data includes detecting a data value stored in a selected memory cell by summing a first current flowing through a first digit line and a second current flowing through a second digit line.
According to another aspect of the embodiments, a cell current can include a summation of the first current flowing through a first digit line, the second current flowing through a second digit line, a third current flowing from a precharge voltage through a virtual ground line, and a fourth current flowing through a fourth digit line.